1. Field of the Invention
The present invention relates to a semiconductor device and to a method of fabricating a semiconductor device. More particularly, the present invention relates to the bonding pad structure of a semiconductor device and to a method of fabricating the same.
This application is a counterpart of, and claims priority to, Korean patent application No. 2000-34902, filed Jun. 23, 2000, the contents of which are incorporated herein by reference in their entirety.
2. Description of the Related Art
As is well known, semiconductor chips are sealed to protect them from external moisture and impact. In addition, a semiconductor device requires a plurality of bonding pads for delivering an electrical signal between its semiconductor chip and external electronics. During assembly, i.e., during a packaging process, the bonding pads of a semiconductor device are electrically connected to lead lines of a lead frame with conductive material such as gold wire. At this time, heat and pressure are applied to the bonding pads for electrically connecting them to the gold wire. As a result, the bonding pads are subject to damage due to the thermal and physical stresses.
Recently, a ball grid array package technique has been widely used to fabricate semiconductor devices. According to the ball grid array package technique, a beam lead is placed directly in contact with the bonding pad. As a result, the bonding pad is likely to suffer from mechanical stress produced by the beam lead and may be damaged. Furthermore, if the ball grid array package is to be made thin, the angle between the beam lead and an upper surface of the bonding pad must be kept to 15 degrees or less. In addition, recent trends in miniaturizing the ball grid array packages have resulted in the bonding pads being down-sized. Accordingly, as the level of the center of a bonding pad becomes lower as compared to a top surface of a passivation layer which exposes the bonding pad, the alignment margin of the beam lead is correspondingly decreased.
U.S. Pat. No. 5,736,791 by Fujiki et al., entitled xe2x80x9cSemiconductor Device And Bonding Pad Structure Thereofxe2x80x9d discloses a bonding pad structure of a semiconductor device having a multi-layered interconnection. The bonding pad structure includes a first metal layer and a second metal layer formed over the first metal layer. An interlayer insulating layer is interposed between the first metal layer and the second metal layer. A plurality of metal plugs penetrate the interlayer insulating layer and electrically interconnect the first metal layer and the second metal layer. The first metal layer is patterned to have a plurality of slits, or the center thereof is etched so as to be open. Accordingly, the surface area of the first metal layer is much less than that of the second metal layer. As a result, most of the second metal layer is directly in contact with the interlayer insulating layer. Thus, the thickness of the bonding pad with which gold wire or beam lead is directly in contact corresponds to only the thickness of the second metal layer. Therefore, an electrical open failure can occur during the process of bonding the gold wire or beam lead.
It is an object of the present invention to provide a reliable bonding pad structure, which provides a relatively large alignment margin for a beam lead.
It is another object of the present invention to provide a method of fabricating a reliable bonding pad structure, which also allows for a large alignment margin when a beam lead is to be bonded thereto.
In order to achieve these objects, the present invention provides/fabricates structure of a semiconductor device, and in particular bonding pad structure, in which there is substantially no height difference (step) between the central region of the top surface of a third conductive layer pattern, to which the beam lead is to be bonded, and the top surface of a third insulating layer patterned to form the via in which the third conductive material layer pattern is formed.
In the present invention, first, second and third conductive layer patterns are disposed on a semiconductor substrate with the second and third conductive layer patterns contacting each other. An insulator is interposed between the first and second conductive layer patterns. In addition, the third conductive layer pattern is electrically connected to the first conductive layer pattern through an opening.
The opening extends through a peripheral edge portion of the second conductive layer pattern and through the insulating layer, and terminates at a peripheral edge portion of the first conductive layer pattern. The opening can consist of an annular slit or can comprise a plurality of discrete holes.
Alternatively, the opening is located outwardly of the second conductive layer pattern, exposes and extends alongside the peripheral edge of the second conductive layer pattern. The opening also extends downwardly through the insulating layer, and terminates at the peripheral edge portion of the first conductive layer pattern. In this case, the second conductive layer pattern is narrower than the first conductive layer pattern. Preferably, the opening consists of an annular slit.
The method of fabricating the above-described bonding pad structure begins with the forming of an insulating layer over a semiconductor substrate on which a first conductive layer pattern has been formed followed by the forming of a second conductive layer pattern on the insulating layer directly above the first conductive layer pattern. The second conductive layer pattern includes an opening extending therethrough at a peripheral portion thereof. The opening exposes the insulating layer covering the first conductive layer pattern. Another insulating layer is formed on the second conductive layer pattern. The insulating layers are then sequentially etched to form a via hole that exposes a central portion of the top surface of the second conductive layer pattern, and the opening, and to extend the opening down to the first conductive layer pattern. Conductive material is deposited to fill the via hole and the extended opening. Thus, a third conductive layer pattern electrically connecting the top surface of the second conductive layer pattern and the peripheral portion of the first conductive layer is formed.
According to another method of the present invention, the second conductive layer pattern is formed on the insulating layer in a pattern narrower than that of the first conductive layer pattern covered by the insulating layer. Another insulating layer is formed on the second conductive layer pattern. The insulating layers are sequentially patterned to form a via hole exposing the entire top surface of the second conductive layer pattern. The via hole includes an opening that exposes the outer peripheral edge of the second conductive layer. The opening extends downwardly and terminates at a peripheral portion of the first conductive layer pattern. Conductive material is deposited to fill the via hole. Thus, a third conductive layer pattern electrically connecting the top surface of the second conductive layer pattern and the peripheral portion of the first conductive layer is formed.